1. Field of the Invention
The present invention relates to a data erasing method and a memory apparatus having a data erasing circuit using such method.
2. Description of the Related Art
Conventionally, a variety of electronic equipment, including computers, houses a memory apparatus that can store and erase data.
This memory apparatus is usually composed of a storage element for storing the data and a data erasing circuit for erasing the data.
As this type of such storage element, there has been used a nonvolatile semiconductor memory cell which is structured to have a control gate and a floating gate on a semiconductor substrate. This storage element stores data based on presence or absence of electrons to be accumulated in the floating gate.
In the case of erasing the data in this storage element, the data is erased by discharging the electrons accumulated in the floating gate through the semiconductor substrate side.
When discharging the electrons accumulated in the floating gate through the semiconductor substrate side, at first, the control gate is placed into its grounded condition, and thereafter, a potential of the semiconductor substrate is boosted by a boost voltage generating circuit housed in the data erasing circuit in order to boost up a potential of the semiconductor substrate up to a predetermined potential.
Thereby, a predetermined erasing voltage is applied between the control gate and the semiconductor substrate, and this erasing voltage is used to discharge the electrons accumulated in the floating gate through the semiconductor substrate side in order to erase data (see, for example, a Patent Document 1: Japanese Patent Laid-Open No. 2000-294658).
In the above-mentioned conventional data erasing method, however, for the reason that the control gate is placed into its grounded condition when boosting the potential of the semiconductor substrate side, the control gate and the semiconductor substrate may cause a capacity coupling, and a part of the electric charges for boosting the potential of the semiconductor substrate leaks into the control gate side.
Hence, it takes long time to boost the potential of the semiconductor substrate, and there has been the problem of increasing the time required to erase data.
There has also been the problem of increasing power consumption during data erasing, because of the above-mentioned leakage of the electric charges.